Integrated circuit (IC) packages are enclosures that house integrated circuit (IC) dies. An IC die is typically a single square or rectangular piece of semiconductor material in which various microelectronic circuits have been formed. An IC package serves to both protect the IC die contained therein from physical and environmental damage and to physically and electrically connect the IC die to a printed circuit board (PCB). The term “IC package” is used herein to describe an IC package without the IC die connected therein. In contrast, the term “IC die package” is used herein to describe an IC package having an IC die connected therein.
In some IC die packages, the IC die is physically and electrically connected to a substrate within the IC package. The substrate is then, in turn, physically and electrically connected to the PCB using a ball grid array, a pin grid array, or various other mechanisms. When the substrate in the IC die package is composed of multiple layers of dielectric material, the IC die package is commonly referred to as a multilayer IC die package.
Multilayer IC die packages may be categorized according to the manner in which the IC die is connected to the substrate. Two such categories are wire bond type packages and flip-chip type packages. In a wire bond type IC die package, the IC die is placed or connected, top-side up, on the substrate and fine wires are used to connect contact pads on the top of the IC die to die pads on the top of the substrate. In contrast, in a flip-chip type package, the IC die is turned or flipped top-side down and the contact pads on the IC die are soldered directly to the die pads on the top of the substrate.
A substrate in a multilayer flip-chip type IC die package may include a number of upper die pads and lower solder pads. The substrate may also include a number of electrical interconnect paths, one disposed between each upper die pad and each lower solder pad. The interconnect paths are composed of electrically conductive signal traces (“traces”) and electrically conductive vias. As such, the term “trace/via path” is used herein to denote this type of interconnection path through the substrate. In general, the traces in the trace/via path are disposed horizontally along or between the various substrate layers. In contrast, the vias in the trace/via path are disposed vertically through the various substrate layers.
Since the IC die is directly connected to the substrate in the multilayer flip-chip IC die package, without the use of wire bonds, the overall conductive signal path through which a signal travels between the IC die and the PCB is substantially shorter in the flip-chip type package than in the wire bond type package. This shorter overall signal path typically corresponds to significantly smaller inductance in the overall signal path in the flip-chip type package, as compared to the wire bond type package. As such, the flip-chip IC die package has generally been preferred to the wire bond IC die package in high-speed systems where lower inductance is generally preferred.
As the density of pin-counts in IC dies has increased, and as the overall form factor of flip-chip packages has decreased, the footprints of the trace/via paths within the substrate of the multilayer flip-chip IC die packages have generally been reduced, so that more interconnect paths may be fit side-by-side within the substrate. This reduction in the footprints of the trace/via paths is achieved, in part, by shortening the lengths of the various traces in the trace/via paths. This, in turn, further reduces the inductance of the overall signal paths in the flip-chip type package.
While lower inductance has, in the past, been thought to be only a benefit in multilayer flip-chip IC die packages, the inductance of the overall signal path may become so low that various signal transmission problems may arise. For example, as the inductance of the overall signal path decreases, the impedance of overall signal path also typically decreases. This is true, because the impedance (Zo) and inductance (L) are generally related as follows: Zo=Sqrt[L/C], where C is the capacitance. If the inductance of the overall signal path is too low, the impedance of the overall signal path may no longer match the impedance of the IC and/or the PCB. When this occurs, signal transmission problems, such as signal reflections and reduced eye height, may occur. These problems may be particularly exacerbated in systems having very high signaling speeds, such as speeds on the order of multiple gigahertz. In these high-speed systems, even a small impedance mismatch may cause severe signaling problems.